Wafer level modeling of electrochemical-mechanical polishing (ECMP)

Materials Research Society Symposium Proceedings

Volumn 991, Issue , 2007, Pages 315-320

  Truque, Daniel ^a   Xiaolin, Xie ^a   Boning, Duane ^a  

^a Massachusetts Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT DENSITY; ELECTROCHEMISTRY; SEMICONDUCTOR DEVICE MODELS; WAFER BONDING;

COPPER THICKNESS; CURRENT DENSITY DISTRIBUTIONS; ELECTROCHEMICAL-MECHANICAL POLISHING (ECMP); WAFER LEVEL MODELING;

CHEMICAL MECHANICAL POLISHING;

EID: 38549124913     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-0991-c11-04     Document Type: Conference Paper

References (7)

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3. F.Q. Liu, et al, "Cu Planarization in Electrochemical Mechanical Planarization". Journal of the Electrochemical Society, 153 (6), pp C377-381, 2006.
4. Lee, Brian, "Modeling of Chemical Mechanical Polishing for Shallow Trench Isolation," Ph.D. Thesis, MIT Dept. of Electrical Engineering and Computer Science, May 2002.
5. F.Q. Liu et al, "High Planarization Efficiency and Wide Process Window Using Electro Chemical Mechanical Planarization (Ecmp™)". Thin Films Group, Applied Materials Inc, Santa Clara, CA, USA.
6. A. Brown, "Flat, Cheap, and Under Control: Applied Materials' New Polishing Technology Could be the Key to the Coming Generation of Microchips," IEEE Spectrum, January 2005
7. J. Lu, C. Rogers, V.P. Manno, A. Philiposian, S. Anjur, and M. Moinpur,"Measurements of slurry film thickness and wafer drag during CMP". Journal of the Electrochemical Society, 151 (4) pp. G241-G247, 2004.