FPGA implementation of evolvable characters recognizer with self-adaptive mutation rates

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4431 LNCS, Issue PART 1, 2007, Pages 286-295

  Wang, Jin ^a   Piao, Chang Hao ^b   Lee, Chong Ho ^a  

^a Inha University   (South Korea)

^b CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS   (China)

Author keywords

[No Author keywords available]

Indexed keywords

EVOLUTIONARY ALGORITHMS; MUTAGENESIS; NEURAL NETWORKS; PATTERN RECOGNITION;

MUTATION PARAMETERS; RATE-BASED APPROACHES; TIME-CONSUMING PROCESS; XILINX VIRTEX XCV2000E;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 38049055185     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-71618-1_32     Document Type: Conference Paper

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