XEEMU: An improved XScale power simulator

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4644 LNCS, Issue , 2007, Pages 300-309

  Herczeg, Zoltán ^a   Kiss, Ákos ^a   Schmidt, Daniel ^b   Wehn, Norbert ^b   Gyimóthy, Tibor ^a  

^a UNIVERSITY OF SZEGED   (Hungary)

^b University of Koblenz Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER UTILIZATION; EMBEDDED SOFTWARE; ENERGY EFFICIENCY; ENERGY UTILIZATION; SYSTEMS ANALYSIS;

ACCURATE MODELING; AVERAGE ERRORS; CYCLE-ACCURATE SIMULATORS; DESIGN DECISIONS; EARLY DESIGN PHASIS; INSTANTANEOUS POWER; POWER SIMULATOR; TOTAL ENERGY CONSUMPTION;

SIMULATORS;

EID: 37849016207     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-74442-9_29     Document Type: Conference Paper

References (15)

1. ARTEMIS Strategic Research Agenda Working Group: Strategic research agenda, 1st edn. (2006)
2. Clark, L.T.: An embedded 32-b microprocessor core for low-power and high-performance applications. IEEE Journal of Solid-State Circuits 36(11), 1599-1608 (2001)
3. Mudge, T., Austin, T., Grunwald, D.: The SimpleScalar-Arm power modeling project, http://www.eecs.umich.edu/~panalyzer/
4. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proceedings of the 27th Annual International Symposium on Computer Architecture (June 2000)
5. Contreras, G., Martonosi, M., Peng, J., Ju, R., Lueh, G.Y.: XTREM: a power simulator for the Intel XScale core. SIGPLAN Not. 39(7), 115-125 (2004)
6. Rabaey, J.M.: The Spice Home Page http://bwrc.eecs.bekeley.edu/Classes/ IcBook/SPICE/
7. Tiwari, V., Malik, S., Wolfe, A.: Power analysis of embedded software: a first step towards software power minimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2(4), 437-445 (1994)
8. Tiwari, V., Malik, S., Wolfe, A., Lee, M.: Instruction-level power analysis and optimization of software. VLSI Signal Processing (13), 223-238 (1996)
9. Varma, A., Debes, E., Kozintsev, I., Jacob, B.: Instruction-level power dissipation in the Intel XScale embedded microprocessor. In: Sudharsanan, S., Bove Jr., V.M., Panchanathan, S. (eds.) Proceedings of SPIE, Embedded Processors for Multimedia and Communications II, San Jose, California, USA, vol. 5683, pp. 1-8. SPIE (2005)
10. Austin, T., Larson, E., Ernst, D.: Simplescalar: an infrastructure for computer system modeling, computer 2(35), 59-67 (2002)
11. Ye, W., Vijaykrishnan, N., Kandemir, M., Irwin, M.J.: The design and use of SimplePower: A cycle-accurate energy estimation tool. In: Proc. of 37th DAC, Los Angeles, California, pp. 340-345 (2000)
12. Intel corporation: Intel 80200 Processor based on Intel XScale Microarchitecture: Developer's Manual. Order Number: 273411-003 (March 2003)
13. Intel corporation: High Performance Memory Controller for the Intel 80200 Processor. Order Number: 273494-001 (March 2001)
14. Department of Software Engineering, University of Szeged: GCC code-size benchmark environment (CSiBE) http://www.csibe.org/
15. Wasabi Systems Inc.: Wasabi Systems GNU tools version 031121 for Intel XS-cale microarchitecture http://www.intel.com/design/intelxscale/dev.tools/ 031121/wasabi_031121.htm