Distributed texture memory in a multi-GPU environment

Proceedings of the SIGGRAPH/Eurographics Workshop on Graphics Hardware

Volumn , Issue , 2006, Pages 31-38

  Moerschell, Adam ^a   Owens, John D ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SHARED MEMORY SYSTEM; TEXTURE MEMORY;

COMPUTER PROGRAMMING; IDENTIFICATION (CONTROL SYSTEMS); SHAPE MEMORY EFFECT;

PROGRAM PROCESSORS;

EID: 36949026866     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283900.1283905     Document Type: Conference Paper

References (18)

1. BLYTHE D.: Private communication. Microsoft, 7 June 2006.
2. CULLER D. E., GUPTA A., SINGH J. P.: Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 1997.
3. CHAN E., NG R., SEN P., PROUDFOOT K., HANRAHAN P.: Efficient partitioning of fragment shaders for multipass rendering on programmable graphics hardware. In Graphics Hardware 2002 (Sept. 2002), pp. 69-78.
4. ELDRIDGE M., IGEHY H., HANRAHAN P.: Pomegranate: A fully scalable graphics architecture. In Proceedings of ACM SIGGRAPH 2000 (July 2000), Computer Graphics Proceedings, Annual Conference Series, pp. 443-454.
5. EVERITT C.: Interactive Order-Independent Transparency. Tech. rep., NVIDIA Corporation, May 2001. http://developer.nvidia.com/object/ Interactive_Order_Transparency.html.
6. HARRIS M. J., COOMBE G., SCHEUERMANN T., LASTRA A.: Physically-based visual simulation on graphics hardware. In Graphics Hardware (Sept. 2002), pp. 109-118.
7. HUMPHREYS G., HOUSTON M., NG R., FRANK R., AHERN S., KIRCHNER P., KLOSOWSKI J.: Chromium: A stream-processing framework for interactive rendering on clusters. ACM Transactions on Graphics 21, 3 (July 2002), 693-702.
8. HOUSTON M., PREETHAM A. J., SEGAL M.: A Hardware F-Buffer Implementation. Tech. Rep. CSTR 2005-05, Stanford University Department of Computer Science, 2005.
9. IGEHY H., STOLL G., HANRAHAN P.: The design of a parallel graphics interface. In Proceedings of SIGGRAPH 98 (July 1998), Computer Graphics Proceedings, Annual Conference Series, pp. 141-150.
10. LEFOHN A. E., KNISS J., STRZODKA R., SENGUPTA S., OWENS J. D.: Glift: Generic, efficient, random-access GPU data structures. ACM Transactions on Graphics 26, 1 (2006), 60-99.
11. LENOSKI D., LAUDON J., GHARACHORLOO K., GUPTA A., HENNESSY J.: The directory-based cache coherence protocol for the DASH multiprocessor. In Proceedings of the 17th Annual International Symposium on Computer Architecture (1990), pp. 148-159.
12. MARK W. R., PROUDFOOT K.: The F-Buffer: A rasterization-order FIFO buffer for multi-pass rendering. In 2001 SIGGRAPH I Eurographics Workshop on Graphics Hardware (2001), pp. 57-64.
13. NVIDIA DEVELOPER RELATIONS: NVIDIA GPUProgramming Guide, 2.4.0 ed., 8July 2005. http: //download. nvidia.com/developer/GPU_Programming_Guide/ GPU_Programming_Guide.pdf.
14. PERSSON E.: Programming for CrossFire™, 2005. http://www.ati.com/developer/.
15. RIFFEL A. T., LEFOHN A. E., VIDIMCE K., LEONE M., OWENS J. D.: Mio: Fast multipass partitioning via priority-based instruction scheduling. In Graphics Hardware 2004 (Aug. 2004), pp. 35-44.
16. SIMONI R.: Implementing a Directory-Based Cache Consistency Protocol. Tech. Rep. CSL-TR-90-423, Stanford University Computer Systems Laboratory, Mar. 1990.
17. VOORHIES D., KIRK D., LATHROP O.: Virtual graphics. In Computer Graphics (Proceedings of SIGGRAPH 88) (Aug. 1988), vol. 22, pp. 247-253.
18. WILLIAMS L.: Pyramidal parametrics. In Computer Graphics (Proceedings of SIGGRAPH 83) (Detroit, Michigan, July 1983), vol. 17, pp. 1-11.