Sequential circuit design for embedded cryptographic applications resilient to adversarial faults

IEEE Transactions on Computers

Volumn 57, Issue 1, 2008, Pages 126-138

  Gaubatz, Gunnar ^a   Savaş, Erkay ^b   Sunar, Berk ^c  

^a Worcester Polytechnic Institute   (United States)

^b SABANCI UNIVERSITY   (Turkey)

^c WORCESTER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Adversarial faults; Data encryption; Error control codes; Error checking; Fault tolerance; Sequential circuits

Indexed keywords

CODES (SYMBOLS); COMPUTER CIRCUITS; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; SECURITY OF DATA; SEQUENTIAL CIRCUITS;

ADVERSARIAL FAULTS; CONTROL LOGIC; CRYPTOGRAPHIC CIRCUITS; DATA ENCRYPTION; ERROR CONTROL CODES; ERROR-CHECKING;

CRYPTOGRAPHY;

EID: 36849018417     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.70784     Document Type: Article

References (21)

1. D. Boneh, R. DeMillo, and R. Lipton, "On the importance of checking cryptographic protocols for faults," in Advances in Cryptology - EuroCrypt'97 (W. Fumy, ed.), vol. 1233 of Lecture Notes in Computer Science, (Heidelberg), pp. 37-51, Springer, 1997. Proceedings.
2. M. Joye, A. Lenstra, and J. Quisquater, "Chinese remaindering based cryptosystem in the presence of faults," Journal of Cryptology, vol. 4, no. 12, pp. 241-245, 1999.
3. E. Biham and A. Shamir, "Differential fault analysis of secret key cryptosystems," in Advances in Cryptology - CRYPTO'97 (B. Kaliski Jr., ed.), no. 1294 in Lecture Notes in Computer Science, (Heidelberg), pp. 513-525, Springer-Verlag, 1997.
4. G. Piret and J. Quisquater, "A differential fault attack technique against SPN structures, with application to the AES and Khazad," in Proc. Int. Workshop on Cryptographic Hardware and Embedded Systems (CHES'03) (C. Walter, (Cetin K.. Koç, and C. Paar, eds.), vol. 2779 of Lecture Notes in Computer Science, (Heidelberg), pp. 77-88, Springer-Verlag, 2003.
5. H. Choukri and M. Tunstall, "Round reduction using faults." 2nd International Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'05), Edinburgh, Scotland, September 2005.
6. M. Joye and S.-M. Yen, "The montgomery powering ladder," in Cryptographic Hardware and Embedded Systems-CHES 2002 (B. Kaliski Jr., Q.K.. Koç, and C. Paar, eds.), vol. 2523 of Lecture Notes in Computer Science, pp. 291-302, Springer-Verlag, 2002.
7. A. Reyhani-Masoleh and M. Hasan, "Towards fault-tolerant cryptographic computations over finite fields," ACM Transactions on Embedded Computing Systems, vol. 3, pp. 593-613, August 2004.
8. G. Gaubatz and B. Sunar, "Robust finite field arithmetic for fault-tolerant public-key cryptography," in 2nd Workshop on Fault Diagnosis and Tolerance in Cryptography - FDTC 2005 (L. Breveglieri and I. Koren, eds.), September 2005.
9. G. Bertom, L. Breveglieri, I. Koren, P. Maistri, and V. Piuri, "On the propagation of faults and their detection in a hardware implementation of the advanced encryption standard," in Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP) (M. Schulte, S. Bhattacharyya, N. Burgess, and R. Schreiber, eds.), (San Jose, CA, USA), pp. 303-314, IEEE Computer Society Press, July 2002.
10. C. Aumüller, P. Bier, W. Fischer, P. Hofreiter, and J.-P. Seifert, "Fault attacks on RSA with CRT: Concrete results and practical countermeasures," in Proceedings of 4th International Workshop on Cryptographic Hardware and Embedded Systems (CHES) (B. Kaliski Jr., Ç. Koç, and C. Paar, eds.), no. 2523 in Lecture Notes in Computer Science LNCS, (Heidelberg), pp. 260-275, Springer-Verlag, 2002.
11. D. Rennels, "Architectures for fault-tolerant spacecraft computers," Proceedings of the IEEE, vol. 66, pp. 1255-1268, Oct 1978.
12. M. Chen and E. A. Trachtenberg, "Permutation codes for the state assignment of fault tolerant sequential machines," in Proc. 10th Digital Avionics Systems Conference, pp. 85-89, IEEE/AIAA, Oct 1991.
13. M. Berg, "Fault tolerant design techniques for asynchronous single event upsets within synchronous finite state machine architectures," in 7th International Military and Aerospace Programmable Logic Devices (MAPLD) Conference, NASA, Sep 2004.
14. D. Pradhan, ed., Fault Tolerant Computing - Theory and Techniques, vol. 1. New Jersey: Prentice-Hall, 1st ed., 1986.
15. S. Skorobogatov and R. Anderson, "Optical fault induction attacks," in Cryptographic Hardware and Embedded Systems - CHES 2002 (B. Kahski, Jr., Ç. K., Koç, and C. Paar, eds.), vol. 2523 of Lecture Notes in Computer Science, (Berlin, Heidelberg, New York), pp. 2-12, Springer-Verlag, August 2002.
16. R. Anderson and M. Kuhn, "Tamper resistance - a cautionary note," in Proceedings of the Second Usenix Workshop on Electronic Commerce, pp. 1-11, USENIX Assoc., USENIX Press, Nov 1996.
17. G. Gaubatz, "Versatile montgomery multiplier architectures," master's thesis, Worcester Polytechnic Institute, Worcester, Massachusetts, May 2002.
18. S. Mitra and E. McCluskey, "Which concurrent error detection scheme to choose?," in Proc. Int. Test Conference (ITC), pp. 985-994, IEEE, IEEE Press, 2000.
19. A. Hopkins Jr. and T. Smith III, "The architecural elements of a symmetric fault-tolerant multiprocessor," IEEE Transactions on Computers, vol. C-24, pp. 498-505, May 1975.
20. H. Helgert and R. Stinaff, "Minimum-distance bounds for binary linear codes," IEEE Transactions on Information Theory, vol. 19, pp. 344-356, May 1973.
21. N. Das and N. Touba, "Weight-based codes and their application to concurrent error detection of multilevel circuits," in VTS'99, 1999.