메뉴 건너뛰기




Volumn 2002-January, Issue , 2002, Pages 303-312

On the propagation of faults and their detection in a hardware implementation of the Advanced Encryption Standard

Author keywords

Fault detection; Hardware

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA PRIVACY; FAULT DETECTION; HARDWARE;

EID: 84948745350     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2002.1030729     Document Type: Conference Paper
Times cited : (21)

References (10)
  • 1
    • 0037880847 scopus 로고    scopus 로고
    • Fault Detection In The Advanced Encryption Standard
    • Ischia, Italy
    • G. Bertoni, L. Breveglieri, I. Koren, V. Piuri, "Fault Detection In The Advanced Encryption Standard," to be presented in MPCS 2002, Ischia, Italy, 2002.
    • (2002) MPCS 2002
    • Bertoni, G.1    Breveglieri, L.2    Koren, I.3    Piuri, V.4
  • 2
    • 84954434858 scopus 로고    scopus 로고
    • The Block Cipher Rijndael
    • Smart-Card Research and Applications, J.-J. Quisquater and B. Schneier, Eds., Springer-Verlag
    • J. Daemen, V. Rijmen, "The Block Cipher Rijndael," Smart-Card Research and Applications, LNCS 1820, J.-J. Quisquater and B. Schneier, Eds., Springer-Verlag, 2000, pp. 288-296.
    • (2000) LNCS , vol.1820 , pp. 288-296
    • Daemen, J.1    Rijmen, V.2
  • 5
    • 3042588040 scopus 로고    scopus 로고
    • An Implementation of DES and AES, secure against some attacks
    • M. Akkar, C. Giraud, "An Implementation of DES and AES, secure against some attacks," Proceeding of CHES 2001, pp. 315-325.
    • Proceeding of CHES 2001 , pp. 315-325
    • Akkar, M.1    Giraud, C.2
  • 6
    • 0010828469 scopus 로고    scopus 로고
    • High Performance single-Chip FPGA Rijndael Algorithm implementations
    • M. McLoone, J. V. McCanny, "High Performance single-Chip FPGA Rijndael Algorithm implementations," Proceeding of CHES 2001, pp. 68-80.
    • Proceeding of CHES 2001 , pp. 68-80
    • McLoone, M.1    McCanny, J.V.2
  • 7
    • 0038557181 scopus 로고    scopus 로고
    • Two Methods of Rijndael Implementation in reconfigurable Hardware
    • V. Fischer, M. Drutarovsky, "Two Methods of Rijndael Implementation in reconfigurable Hardware," Proceeding of CHES 2001, pp. 81-96.
    • Proceeding of CHES 2001 , pp. 81-96
    • Fischer, V.1    Drutarovsky, M.2
  • 8
    • 0038218553 scopus 로고    scopus 로고
    • Architectural Optimization for a 1,82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
    • H. Kuo and I. Verbauwhede, "Architectural Optimization for a 1,82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm," Proceeding of CHES 2001, pp. 53-67.
    • Proceeding of CHES 2001 , pp. 53-67
    • Kuo, H.1    Verbauwhede, I.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.