Subthreshold 1-bit full adder cells in sub-100 nm technologies

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 514-515

  Moalemi, Vahid ^a   Afzali Kusha, Ali ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; NATURAL FREQUENCIES;

ADDER CELLS; POWER DELAY PRODUCT; SUPPLY VOLTAGE;

ELECTRIC BATTERIES;

EID: 36349024567     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.93     Document Type: Conference Paper

References (4)

1. H. Soeleman, K. Roy, and B. C. Paul, "Robust subthreshold logic for ultra-low power operation," IEEE Trans. VLSI Syst., vol. 9, pp. 90-99, Feb. 2001.
2. Hung Tien Bui, Yuke Wang, and Yingtao Jiang, "Design and Analysis of Low-Power 10-Transistor Full Adders Using Novel XOR-XNOR Gates," IEEE Trans. on circuits and systems-II: analog and digital signal processing, vol. 49, no. 1, January 2002 pp, 25-30.
3. N. Zhuang and H. Wu, "A new design of the CMOS full adder," IEEEJ. of Solid-State Circuits, vol. 27, pp. 840-844, May 1992.
4. H. T. Bui, A. K. Al-Sheraidah, and Y. Wang, "Design and analysis of 10-transistor full adders using novel XOR-XNOR gates," in Proc. Int. Conf. Signal Processing 2000 (Wold Computer Congress), Beijing, China, Aug. 2000.