DFM methodology for automatic layout hot spot removal

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6607, Issue PART 1, 2007, Pages

  Wong, Tom ^a   Ravikumar, Ravi ^a  

^a Takumi Technology Corporation   (United States)

Author keywords

CAA; Cell; Compaction; Defect; DFM; GDSII; Layout optimization; Layouts; Library; Yield enhancement

Indexed keywords

CHIP SCALE PACKAGES; INTEGRATED CIRCUIT TESTING; NANOTECHNOLOGY; OPTIMIZATION;

DESIGN-FOR-MANUFACTURING (DFM); LAYOUT OPTIMIZATION; YIELD ENHANCEMENT;

INTEGRATED CIRCUIT LAYOUT;

EID: 36248935507     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.728939     Document Type: Conference Paper

References (4)

1. Peter Rabkin, "DFM for Advanced Technology Nodes: Fabless View," Future Fab International, Vol. 20, 2006.
2. S. Inoue, S.Kobayashi, S.Kyoh, T.Kotani, T.Inazu, A.Ikeuchi, Y. Urakawa, et al, "Development of Hot Spot Fixer", Proc. SPIE, Vol. 6156, 2006.
3. Aaron Hand, "Litho Simulation Enables the Leading Edge," Semiconductor International, 2006.
4. Franklin M. Schellenberg, "Resolution Enhancement Technology: the Past, the Present, and Extensions for the Future," Emerging Lithographic Technologies VIII, Proc. SPIE, Vol. 5374, 2004.