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Volumn 2, Issue 2, 2005, Pages 109-130

Adapting Branch-Target Buffer to Improve The Target Predictability of Java Code

Author keywords

Branch prediction; Branch target buffer (BTB); Computer architecture; Design; Java; Performance; Pipelined processor

Indexed keywords


EID: 36048997661     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1071604.1071605     Document Type: Article
Times cited : (16)

References (23)
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  • 8
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  • 10
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    • A study of the cache and branch performance issues with running java on current hardware platforms
    • Hsieh, C. H. A., Conte, M. T., Johnson, T. L., Gyllenhaal, J. C., and Hwu, W. W. 1997. A study of the cache and branch performance issues with running java on current hardware platforms. In Proceedings of Compcon. 211-216.
    • (1997) Proceedings of Compcon , pp. 211-216
    • Hsieh, C.H.A.1    Conte, M.T.2    Johnson, T.L.3    Gyllenhaal, J.C.4    Hwu, W.W.5
  • 12
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    • Branch prediction strategies and branch-target buffer design
    • Lee, J. and Smith, A. 1984. Branch prediction strategies and branch-target buffer design. IEEE Computer 17, 1
    • (1984) IEEE Computer , vol.17 , Issue.1
    • Lee, J.1    Smith, A.2
  • 18
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    • CACTI2.0: An integrated cache timing and power model
    • July, 2000.
    • Reinman, G. and Jouppi, N. P. 2000. CACTI2.0: An integrated cache timing and power model. WRL Research Report, July, 2000.
    • (2000) WRL Research Report
    • Reinman, G.1    Jouppi, N.P.2
  • 20
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.