A reconfigurable logic-based processor for the SCAN image and video encryption algorithm

International Journal of Parallel Programming

Volumn 31, Issue 6, 2003, Pages 489-506

  Kachris, C ^a   Bourbakis, N ^b   Dollas, A ^a  

^a TECHNICAL UNIVERSITY OF CRETE   (Greece)

^b WRIGHT STATE UNIVERSITY   (United States)

Author keywords

Block cipher; Cryptography; Image encryption; Reconfigurable logic

Indexed keywords

ALGORITHMS; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE PROCESSING; PROGRAM PROCESSORS; RANDOM ACCESS STORAGE; SOFTWARE ENGINEERING;

BLOCK CIPHER; IMAGE ENCRYPTION; RECONFIGURABLE LOGIC; VIDEO ENCRYPTION;

PARALLEL PROCESSING SYSTEMS;

EID: 3543148897     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:IJPP.0000004512.53221.ff     Document Type: Conference Paper

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