Via interconnections for wafer level packaging: Impact of tapered via shape and via geometry on product yield and reliability

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 858-863

  Shariff, Dzafir ^a   Suthiwongsunthorn, Nathapong ^a   Bieck, Florian ^a   Leib, Jürgen ^a  

^a SCHOTT Advanced Packaging Singapore Pte Ltd   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

IMAGE SENSORS; INTERCONNECTION NETWORKS; LITHOGRAPHY; OPTICAL IMAGE STORAGE; PLASMA ETCHING; RELIABILITY; WAFER BONDING;

ADVANCED PACKAGING; BOND PADS; PRODUCT YIELD; THROUGH SILICON VIA (TSV); WAFER LEVEL PACKAGING;

ELECTRONICS PACKAGING;

EID: 35348903765     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373899     Document Type: Conference Paper

References (4)

1. J. Leib and M. Topper, "New Wafer -Level Packaging Technology Using Silicon -Via -Contacts for Optical And Other Sensor Applications," 54th Electronic Components and Technology Conf, Las Vegas, 2004.
2. G. Viswanadam, F. Bieck and N. Suthiwongsunthorn, "Novel Wafer Level Package Technology Studies for Image Sensor Devices," Electronic Packaging and Technology Conf, Singapore, 2005.
3. Ha-Duong Ngo, A. Hiess, V. Seidemann, D. Studzinski, M. Lange, J. Leib, D. Shariff, H. Ashraf , M. Steel, L. Atabo, J. Reast, "Plasma Etching of Tapered Features in Silicon for MEMS and Wafer Level Packaging Applications," Proc International MEMS Conference, Singapore, 2006.
4. Lieberman, A.M., Principles of Plasma Discharges and Materials Processing. John Wiley & Sons, New York, 1994.