Effect of temperature on the drop reliability of wafer-level chip scale packaged electronics assemblies

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2007, Pages 940-945

  Mattila, T T ^a   James, R J ^a   Nguyen, L ^b   Kivilahti, J K ^a  

^a AALTO UNIVERSITY   (Finland)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CRACK PROPAGATION; PORTABLE EQUIPMENT; RELIABILITY; THERMOMECHANICAL TREATMENT; WAFER BONDING;

COMPLEX LOADINGS; DROP RELIABILITY; MECHANICAL LOADINGS; REAL OPERATIONAL LOADING CONDITIONS;

ELECTRONIC EQUIPMENT;

EID: 35348861779     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373909     Document Type: Conference Paper

References (4)

1. JESD22-B111, Board Level Drop Test Method of Components for Handheld Electronic Products, JEDEC Solid State Technology Association, 2003, p. 16.
2. T. T. Mattila, P. Marjamäki, and J. K. Kivilahti, "Reliability of CSP Components Under Mmechanical Shock Loading", IEEE Transactions on Components and Packaging Technologies,19, 4, (2006), pp. 787 - 795.
3. T. T. Mattila, Reliability of High-Density Lead-Free Solder Interconnections under Thermal Cycling and Mechanical Shock Loading, Espoo, 2005, HUT-EPT-13, Otamedia, p. 202. (http://lib.tkk.fi/Diss/2005/isbn9512279843/ )
4. P. Marjamäki, Vibration Test as a New Method for Studying The Mechanical Reliability of Solder Interconnections Under Shock Loading Conditions, Doctoral Thesis, HUT, (to be published 2007).