Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms

Annual ACM Symposium on Parallelism in Algorithms and Architectures

Volumn , Issue , 2007, Pages 348-357

  Furtak, Timothy ^a   Amaral, José Nelson ^a   Niewiadomski, Robert ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

Instruction level parallelism; Quicksort; SIMD; Sorting; Sorting networks; Vectorization

Indexed keywords

ALGORITHMS; PROGRAM PROCESSORS; SECURITY OF DATA; SET THEORY; SORTING; THRESHOLD ELEMENTS;

INSTRUCTION-LEVEL PARALLELISM; QUICKSORT; SINGLE INSTRUCTION MULTIPLE DATA (SIMD); SORTING NETWORKS;

PARALLEL PROCESSING SYSTEMS;

EID: 35248837401     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1248377.1248436     Document Type: Conference Paper

References (21)

1. K. E. Batcher. Sorting networks and their applications. In AFIPS Spring Joint Computing Conference, pages 307-314, 1968.
2. L. Bishop, D. Eberly, T. Whitted, M. Finch, and M. Shantz. Designing a PC game engine. IEEE Computer Graphics and Applications, 18(1):46-53, 1998.
3. D. Bitton, D. J. DeWitt, D. K. Hsiao, and J. Menon. A taxonomy of parallel sorting. Computing Surveys, 16(3):287-318, September 1984.
4. J. D. Frens and D. S. Wise. Auto-blocking matrix-multiplication or tracking BLAS3 performance from source code. In Principples and Practice of Parallel Programming PPoPP, pages 206-216, Las Vegas, Nevada, 1997.
5. M. Frigo. A fast Fourier transform compiler. In Programming Language Design and Implementation PLDI, pages 169-180, Atlanta, GA, June 1999.
6. Intel. IA-32 Intel®64 and ai-32 architectures software developer's manual volume 1: Basic architecture. http://www.intel.com/design/processor/ manuals/253665.pdf, 2007.
7. Douglas W. Jones. An empirical comparison of priority-queue and event-set implementations. Commun. ACM, 29(4):300-311, 1986.
8. Donald Ervin Knuth. The Art of Computer Programming, Vol. 3 - Sorting and Searching. Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1973.
9. A. LaMarca, and R. E. Ladner. The influence of caches on the performance of heaps. ACM Journal of Experimental Algorithms, 1:4, 1996.
10. A. LaMarca and R. E. Ladner. The influence of caches on the performance of sorting. In SODA: ACM-SIAM Symposium on Discrete Algorithms (A Conference on Theoretical and Experimental Analysis of Discrete Algorithms), 1997.
11. X. Li, M. Garzaran, and D. Padua. A dynamically tuned sorting library. In Code Generation and Optimization CGO, pages 111-122, Palo Alto, CA, 2004.
12. X. Li, M. J. Garzarán, and D. Padua. Optimizing sorting with genetic algorithms. In Code Generation and Optimization CGO, pages 99-110, San Jose, CA, March 2005.
13. D. Nuzman, I. Rosen, and A. Zaks. Auto-vectorization of interleaved data for SIMD. In Programming language design and implementation PLDI, pages 132-143, 2006.
14. A. Ranade, S. Kothari, and R. Udupa. Register efficient mergesorting. In High Performance Computing - HiPC, volume 1970 of LNCS, pages 96-103. Springer, 2000.
15. Gang Ren, Peng Wu, and David Padua. Optimizing data permutations for SIMD devices. In Programming language design and implementation PLDI, pages 118-131, 2006.
16. Xipeng Shen and Chen Ding. Adaptive data partition for sorting using probability distribution. In ICPP '04: Proceedings of the 2004 International Conference on Parallel Processing (ICPP'04), pages 250-257, Washington, DC, USA, 2004. IEEE Computer Society.
17. H. J. Siegel. The universality of various types of SIMD machine interconnection networks. In Proceedings of the 4th Annual Symposium on Computer Architecture, pages 23-25, Silver Spring, MD, March 1977. ACM SIGARCH/IEEE-CS.
18. S. A. A. Touati. Register saturation in instruction level parallelism. International Journal of Parallel Programming, 33(4):393-449, 2005.
19. R-. Whaley, A. Petitet, and J. Dongarra. Automated empirical optimizations of sotware and the ATLAS project. Parallel Computing, 27(1-2):3-35, 2001.
20. R. Wickremesinghe, L. Arge, J. S. Chase, and J. S. Vitter. Efficient sorting using registers and caches. ACM Journal of Experimental Algorithmics, 7:9, 2002.
21. J. Xiong, J. Johnson, R. Johnson, and D. Padua. SPL: A language and compiler for DSP algorithms. In Programming Language Design and Implementation PLDI, pages 298-308, Snowbird, Utah, June 2001.