Cluster-driven hardware/software partitioning and scheduling approach for a reconfigurable computer system

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2778, Issue , 2003, Pages 1071-1074

  Wiangtong, Theerayod ^a   Cheung, Peter Y K ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CLUSTERING ALGORITHMS; HARDWARE; RECONFIGURABLE HARDWARE; SCHEDULING; SCHEDULING ALGORITHMS;

CO-DESIGN SYSTEMS; DEGREE OF PARALLELISM; HARDWARE/SOFTWARE PARTITIONING; PRE-PROCESSING STEP; RECONFIGURABLE COMPUTER; RECONFIGURABLE RESOURCES; SCHEDULING SYSTEMS; TWO-PHASE CLUSTERING;

COMPUTER HARDWARE;

EID: 35248822741     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_122     Document Type: Article

References (4)

1. Srinivasan, V.; Govindarajan, S.; Vemuri, R., "Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, pp. 140-158, 2001.
2. Palis, M.A.; Liou, J.-C.; Wei, D.S.L., "A greedy task clustering heuristic that is provably good", Parallel Architectures, Algorithms and Networks, 1994.
3. Wiangtong, T.; Cheung, P.Y.K.; Luk, W., "Comparing Three Heuristic Search Methods for Functional Partitioning in HW-SW Codesign", International Journal on Design Automation for Embedded Systems, vol. 6, pp. 425-449, July 2002.
4. Haynes, S.D.; others, a., "UltraSONIC: A Reconfigurable Architecture for Video Image Processing", Field-Programmable Logic and Applications (FPL), 2002.