-
1
-
-
0032630134
-
Symbolic Model Checking Using SAT Procedures instead of BDDs
-
A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, and Y. Zhu, "Symbolic Model Checking Using SAT Procedures instead of BDDs," in Proceedings of the 36th Design Automation Conference, 1999.
-
(1999)
Proceedings of the 36th Design Automation Conference
-
-
Biere, A.1
Cimatti, A.2
Clarke, E.M.3
Fujita, M.4
Zhu, Y.5
-
2
-
-
0002470263
-
Symbolic Model Checking without BDDs
-
A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu, "Symbolic Model Checking without BDDs," in TACAS'99, 1999.
-
(1999)
TACAS'99
-
-
Biere, A.1
Cimatti, A.2
Clarke, E.M.3
Zhu, Y.4
-
3
-
-
0022769976
-
Graph-Based Algorithms for Boolean Function Manipulation
-
August
-
R. E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," in IEEE Transactions on Computers, 35(8), pp. 677-691, August 1986.
-
(1986)
IEEE Transactions on Computers
, vol.35
, Issue.8
, pp. 677-691
-
-
Bryant, R.E.1
-
5
-
-
77957101066
-
Location on Networks
-
North-Holland
-
M. Labbe, D. Peeters, and J. -F Thisse, "Location on Networks," in Handbooks in OR & MS, North-Holland, pp. 551-624, 1995.
-
(1995)
Handbooks in OR & MS
, pp. 551-624
-
-
Labbe, M.1
Peeters, D.2
Thisse, J.F.3
-
6
-
-
0028413136
-
Symbolic Model Checking for Sequential Circuit Verification
-
April
-
J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill, "Symbolic Model Checking for Sequential Circuit Verification," in IEEE Transactions on Computer-Aided Design of Integrated Circuits 13(4), pp. 401-424, April 1994.
-
(1994)
IEEE Transactions on Computer-aided Design of Integrated Circuits
, vol.13
, Issue.4
, pp. 401-424
-
-
Burch, J.R.1
Clarke, E.M.2
Long, D.E.3
McMillan, K.L.4
Dill, D.L.5
-
7
-
-
0022706656
-
Automatic Verification of Finite-state Concurrent Systems Using Temporal Logic Specifications
-
E. M. Clarke, E. A. Emerson, and A. P. Sistla, "Automatic Verification of Finite-state Concurrent Systems Using Temporal Logic Specifications," in ACM Transactions on Programming Languages and Systems, 8(2), pp. 244-263, 1986.
-
(1986)
ACM Transactions on Programming Languages and Systems
, vol.8
, Issue.2
, pp. 244-263
-
-
Clarke, E.M.1
Emerson, E.A.2
Sistla, A.P.3
-
10
-
-
0035215350
-
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs
-
A. Gupta, Z. Yang, P. Ashar, L. Zhang, and S. Malik, "Partition- Based Decision Heuristics for Image Computation Using SAT and BDDs," in Proceedings of the International Conference on Computer-Aided Design, 2001.
-
(2001)
Proceedings of the International Conference on Computer-aided Design
-
-
Gupta, A.1
Yang, Z.2
Ashar, P.3
Zhang, L.4
Malik, S.5
-
11
-
-
0042194878
-
Efficient Computation of Recurrence Diameters
-
D. Kroening, and O. Strichman, "Efficient Computation of Recurrence Diameters," in 4th International Conference on Verification, Model Checking, and Abstract Interpretation, 2003.
-
(2003)
4th International Conference on Verification, Model Checking, and Abstract Interpretation
-
-
Kroening, D.1
Strichman, O.2
-
12
-
-
0034852165
-
Chaff: Engineering an Efficient SAT solver
-
M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT solver," in Proceedings of the Design Automation Conference, 2001.
-
(2001)
Proceedings of the Design Automation Conference
-
-
Moskewicz, M.1
Madigan, C.2
Zhao, Y.3
Zhang, L.4
Malik, S.5
-
18
-
-
25144467851
-
A Practical Approach to Cycle Bound Estimation for Property Checking
-
June
-
C.-C. Yen, K.-C Chen, and J.-Y. Jou, "A Practical Approach to Cycle Bound Estimation for Property Checking," in 11th IEEE/ACM International Workshop on Logic Synthesis, pp. 149-154, June 2002.
-
(2002)
11th IEEE/ACM International Workshop on Logic Synthesis
, pp. 149-154
-
-
Yen, C.-C.1
Chen, K.-C.2
Jou, J.-Y.3
|