GAL sification of IEEE 802.11a baseband processor

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3254, Issue , 2004, Pages 258-267

  Krstić, Miloš ^a   Grass, Eckhard ^a  

^a IMP   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

BASEBAND PROCESSORS; CLOCK GENERATOR; DIGITAL SYSTEM; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS; IEEE802.11A; INTERNAL PIPELINES; POWER ESTIMATIONS; TIME-OUTS;

CLOCKS;

EID: 35048846229     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30205-6_28     Document Type: Article

References (7)

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2. S. Moore, G. Taylor, R. Mullins, P. Cunningham, P. Robinson, Self Calibrating Clocks for Globally Asynchronous Locally Synchronous System, In Proc. International Conference on Computer Design (ICCD), September 2000.
3. M. Krstić, E. Grass, New GALS Technique for Datapath Architectures, In Proc. International Workshop PATMOS, pp. 161-170, September 2003.
4. IEEE P802.11a/D7.0, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High Speed Physical Layer in the 5 GHz Band, July 1999.
5. E. Grass, K. Tittelbach-Helmrich, U. Jagdhold, A. Troya, G. Lippert, O. Krüger, J. Lehmann, K. Maharatna, K. Dombrowski, N. Fiebig, R. Kraemer, P. M̈ḧnen, On the SingleChip Implementation of a Hiperlan/2 and IEEE 802.11a Capable Modem, IEEE Personal Communications, Vol. 8, No. 6, pp. 48 - 57, 2001.
6. J. Seizovic, Pipeline Synchronization, In Proc. International Symposium of Advanced Research in Asynchronous Circuits and Systems, pp 87-96, No v 1994.
7. K. Yun, D. Dill, Automatic synthesis of extended burst-mode circuits: Part I and II, IEEE Transactions on Computer-Aided Design, 18(2), pp. 101-132, February 1999.