Formal verification of digital circuits using symbolic model checking

Informacije MIDEM

Volumn 30, Issue 3, 2000, Pages 153-160

  Časar, Aleš ^a   Brezočnik, Zmago ^a   Kapus, Tatjana ^a  

^a UNIVERSITY OF MARIBOR   (Slovenia)

Author keywords

BDD; Binary decision diagrams; Characteristic functions; Computation Tree Logic; Computer science; CTL; Digital circuits; Electrotechnics; Fairness constraints; Final state machines; Formal verification; FSM; Reachable states; Transition relations

Indexed keywords

EID: 0347934736     PISSN: 03529045     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

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2. Randal E. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Transactions on Computers, C-35(8):677-691, August 1986.
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4. E. M. Clarke, E. A. Emerson, and A. P. Sistla. Automatic Verification of Finite-State Concurrent Systems using Temporal Logic Specifications. ACM Transactions on Programming Languages and Systems, 8(2):244-263, April 1986.
5. Aleš Časar. Verification of Finite State Machines with Symbolic Model Checking. Master's thesis. University of Maribor, Faculty of Electrical Engineering and Computer Science, Maribor, Slovenia, June 1998. In Slovene.
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7. Aleš Časar, Zmago Brezočnik, and Tatjana Kapus. Exploiting Partitioned Transition Relations for Efficient Symbolic Model Checking in CTL. In Penny Storms, editor, Proceedings of the European Design & Test Conference ED&TC'96, pages 606-606, Paris, France, March 1996. IEEE Computer Society Press.
8. Aleš Časar, Zmago Brezočnik, and Tatjana Kapus. Fairness Constraints in Symbolic CTL Model Checking. In Baldomir Zajc and Franc Solina, editors, Proceedings of the seventh Electrotechnical and Computer Science Conference ERK'98, volume B, pages 39-42, Portorož, Slovenia, September 1998. In Slovene.
9. Aleš Časar, Zmago Brezočnik, and Tatjana Kapus. Symbolic Model Checking of Finite State Machines with CTL. In Baldomir Zajc and Franc Solina, editors, Proceedings of the fifth Electrotechnical and Computer Science Conference ERK'96, volume A, pages 51-54, Portorož, Slovenia, September 1996. In Slovene.
10. Aleš Časar, Robert Meolic, Zmago Brezočnik, and Bogomir Horvat. Representation of Boolean Functions with ROBDDs. Electrotechnical Review, 59(5):299-307, December 1992. In Slovene.
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