Emitter layer design for high-speed InP HBTs with high reliability

Conference Proceedings - International Conference on Indium Phosphide and Related Materials

Volumn , Issue , 2007, Pages 441-442

  Kashio, Norihide ^a   Kurishima, Kenji ^a   Fukai, Yoshino K ^a   Yamahata, Shoji ^a   Miyamoto, Yasuyuki ^b  

^a NTT CORPORATION   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT DENSITY; DOPING (ADDITIVES); INDIUM PHOSPHIDE;

CURRENT GAIN; EMITTER LAYER DESIGN; STRESS CURRENT DENSITY;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 34748926350     PISSN: 10928669     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICIPRM.2007.381219     Document Type: Conference Paper

References (2)

1. Y. K. Fukai, et al., IPRM2005, pp. 339-342.
2. M. Ida, et al., IEICE Trans. Electron., vol. E86-C, pp. 1923-1928, 2003.