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Volumn , Issue , 2006, Pages 389-392

X/Ku band CMOS LNA design techniques

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; GAIN MEASUREMENT; NOISE FIGURE;

EID: 34748921926     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320956     Document Type: Conference Paper
Times cited : (47)

References (6)
  • 1
    • 0034270887 scopus 로고    scopus 로고
    • A low-voltage 5.1-5.8GHz image-reject downconverter RFIC
    • Sept
    • J. R. Long, "A low-voltage 5.1-5.8GHz image-reject downconverter RFIC," IEEE J. Solid-State Circuits,vol. 35, pp. 1320-1328, Sept. 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , pp. 1320-1328
    • Long, J.R.1
  • 4
    • 39049144669 scopus 로고    scopus 로고
    • FET Noise Modeling and LNA Design
    • April
    • S. S. Taylor, "FET Noise Modeling and LNA Design," talk at UC Berkeley, April 2004.
    • (2004) talk at UC Berkeley
    • Taylor, S.S.1
  • 5
    • 0031147079 scopus 로고    scopus 로고
    • A 1.5-V, 1.5-GHz CMOS low noise amplifier
    • May
    • D. K. Shaeffer, et al., "A 1.5-V, 1.5-GHz CMOS low noise amplifier," IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , pp. 745-759
    • Shaeffer, D.K.1
  • 6
    • 0036309613 scopus 로고    scopus 로고
    • Modeling of passive elements with ASITIC
    • A. M. Niknejad, "Modeling of passive elements with ASITIC," RFIC Digest of Papers, 2002, pp. 303-306.
    • (2002) RFIC Digest of Papers , pp. 303-306
    • Niknejad, A.M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.