Combinational equivalence checking for threshold logic circuits

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 102-107

  Gowda, Tejaswi ^a   Vrudhula, Sarma ^a   Konjevod, Goran ^a  

^a ARIZONA STATE UNIVERSITY   (United States)

Author keywords

EDA; Equivalence checking; Nano devices; Threshold logic

Indexed keywords

AUTOMATION; BOOLEAN ALGEBRA; COMBINATORIAL MATHEMATICS; COMPUTER AIDED DESIGN; LOGIC DESIGN; THRESHOLD LOGIC;

BOOLEAN LOGIC; EQUIVALENCE CHECKING; NANO DEVICES;

LOGIC CIRCUITS;

EID: 34748907118     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228813     Document Type: Conference Paper

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