Clock-jitter reduction techniques in continuous time delta-sigma modulators

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Volumn , Issue , 2007, Pages 117-118

  Zare Hoseini, Hashem ^a   Kale, Izzet ^a,b  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

^b EASTERN MEDITERRANEAN UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; DIGITAL TO ANALOG CONVERSION; ELECTRIC POWER UTILIZATION; JITTER;

CLOCK-JITTER REDUCTION; JITTER SUPPRESSION;

DELTA SIGMA MODULATION;

EID: 34748892972     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2006.258138     Document Type: Conference Paper

References (7)

1. H. Zare-Hoseini and I. Kale, "Continuous Time Delta Sigma Modulators with Reduced Clock Jitter Sensitivity," IEEE" Int. Symp. on Circuits and Systems, May 2006.
2. S. Yan and E. Sánchez-Sinencio, "Continuous-Time EA Modulator with 88-dB Dynamic Range and 1.1-MHz Signal Band-width," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 75-86, Jan 2004.
3. B. M. Putter, "EAADC with finite impulse response feedback DAC," IEEE Int. Solid-State Circuits Conf, pp. 76-77. Feb 2004.
4. O. Oliaei, "Continuous-time sigmardelta modulator incorporating semi-digital FIR filters," IEEE Int. Symp. on Circuits and Systems, pp. 957-960, May 2003.
5. Younis Saed G, Butterfield D. K., "Method and apparatus for eliminating clock-jitter in continuous-time delta-sigma analogr-todigital converter'' Australian Patent 0 036 750, June 2000.
6. A. Eshraghi et. al.," High Performance Delta-Sigma ADC Using A Feedback.NRZ SIN Signal," US patent, no. 646268.7B1, Oct. 2002.
7. H. Zarer-Hoseini, I. Kale, C. S. Morling "Technique and Method for Suppressing Clock-Jitter in Continuous-Time Delta-Sigma Modulators," International Patent App., PCT/GB2005/004832.