Integration of high performance and low cost Cu/ultra low-k SiOC(k=2.0) interconnects with self-formed barrier technology for 32nm-node and beyond

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 67-69

  Ohoka, Y ^a   Ohba, Y ^a   Isobayashi, A ^a   Hayashi, T ^a   Komai, N ^a   Arakawa, S ^a   Kanamura, R ^a   Kadomura, S ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER ALLOYS; ELECTROMIGRATION; INTEGRATION; LITHOGRAPHY; SILICON CARBIDE; STRESS ANALYSIS;

DAMASCENE; PORE-SEALING PROCESS; SIOC; STRESS-INDUCED VOIDING;

OPTICAL INTERCONNECTS;

EID: 34748874843     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382351     Document Type: Conference Paper

References (7)

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3. A. Isobayashi et al., Proc. of IEDM (2004) pp 953-956
4. T. Usui et al., Proc. of IITC(2005) pp.188-190
5. Y. Ohoka et al., Proc. of VLSI Tech. (2006) pp 140-141
6. R. Kanamura et al., Proc. of VLSI Tech. (2003) pp107-108
7. S. Arakawa et al., Proc. of IITC (2006) pp.210-212