Capacitance reduction effect using capping-layer removal process for porous low-k (k=2.5)/Cu system toward 45nm technology node

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 144-146

  Ohashi, N ^a   Soda, E ^a   Suzuki, T ^a   Kondo, S ^a   Oda, N ^a   Ogawa, S ^a   Saito, S ^a  

^a SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DRY ETCHING; ELECTRIC POWER SYSTEM INTERCONNECTION; INTEGRATED CONTROL; METALLIZING; NANOTECHNOLOGY; POROUS MATERIALS;

CAPPING LAYERS; DAMAGED INTERFACE LAYERS;

CAPACITANCE;

EID: 34748826344     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382365     Document Type: Conference Paper

References (5)

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3. K. Yoneda et al, Proc. IITC, pp.184 (2006)
4. N.Ohashi et al, Proc. IEDM, pp.857 (2003)
5. S. Kondo et al, Proc. IITC, pp.164 (2006)