A CMOS image sensor with a column-level multiple-ramp single-slope ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 506-508

  Snoeij, M F ^a   Donegan, P ^b   Theuwissen, A J P ^a,c   Makinwa, K A A ^a   Huijsing, J H ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b DALSA Corporation   (Canada)

^c DALSA Semiconductors   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; POWER CONVERTERS; SOFTWARE PROTOTYPING;

MULTIPLE-RAMP SINGLE-SLOPE (MRSS); SINGLE-SLOPE ADC; SINGLE-SLOPE ARCHITECTURE;

IMAGE SENSORS;

EID: 34548862595     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373516     Document Type: Conference Paper

References (3)

1. T. Sugiki et al., "A 60mW 10b CMOS Image Sensor with Column-to-Column FPN Reduction," ISSCC Dig. Tech. Papers, pp. 108-109, Feb., 2000.
2. Y. Nitta et al., "High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor," ISSCC Dig. Tech. Papers, pp. 500-501, Feb., 2006.
3. P. Holloway, "A Trimless 16b Digital Potentiometer," ISSCC Dig. Tech. Papers, pp. 66-67, Feb., 1984.