A 12-bit ratio-independent algorithmic ADC for a capacitive sensor interface

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 1713-1716

  Järvinen, Jere A M ^a   Saukoski, Mikko ^a   Halonen, Kari ^a  

^a AALTO UNIVERSITY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; FLIP FLOP CIRCUITS; NETWORK ARCHITECTURE; OPTIMIZATION; SENSOR NETWORKS;

BIASED OPERATIONAL AMPLIFIERS; CAPACITIVE SENSOR INTERFACES; DIGITAL LOGIC; DYNAMIC LATCH;

ANALOG TO DIGITAL CONVERSION;

EID: 34548857951     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.377924     Document Type: Conference Paper

References (4)

1. P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, "A ratio-independent algorithmic analog-to-digital conversion technique," IEEE J. Solid-State Circuits, vol. SC-19, no. 6, pp. 828-836, Dec. 1984.
2. J. A. M. Järvinen, M. Saukoski, and K. Halonen, "A 12-bit 32/μW ratio-independent algorithmic ADC," in Proc. Symposium on VLSI Circuits, 15-17 June 2006, pp. 58-59.
3. B. G. Lee and S. Yan, "A new ratio-independent A/D conversion technique for high-resolution pipeline A/D converters," in Proc. Int. Symp. Circuits Syst., vol. 3, 23-26 May 2005, pp. 1960-1963.
4. R. Harjani, R. Heineke, and F. Wang, "An integrated low-voltage class AB CMOS OTA," IEEE J. Solid-State Circuits, vol. 34, no. 2, pp. 134-142, Feb. 1999.