Phase-change memory development status

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2007, Pages

  Schrott, Alejandro ^a,c   Lung, Hsiang Lan ^a,b   Happ, Thomas ^a,b   Lam, Chung ^a,c  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b Macronix ^*

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

STORAGE ALLOCATION (COMPUTER); VLSI CIRCUITS;

DEVELOPMENT STATUS; ROAD MAP;

PHASE CHANGE MEMORY;

EID: 34548853404     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2007.378940     Document Type: Conference Paper

References (7)

1. S. R. Ovshinsky, "Reversible Electrical Switching Phenomena in Disordered Structures," Phys. Rev. Lett. Vol. 21, 1968, p. 1450.
2. S. Lai, T. Lowrey, "OUM - A 180 nm nonvolatile memory cell element technology for stand-alone and embedded applications," 36.5, IEDM Tech. Dig., 2001.
3. Y. C., Chen, et. al., "Ultra-Thin Phase-Change Bridge Memory Device using GeSb," 30.3, IEDM Tech. Dig., 2006.
4. T. D. Happ, et al., "Novel One-Mask Self-Heating Pillar Phase-change Memory,'' Symp. VLSI Tech., 2006.
5. W. Czubatyj et al, "Current Reduction in Ovonic Memory Devices," E*PCOS 2006.
6. S. J. Ahn et al, "Highly Reliable 50nm Contact Cell Technology for 256Mb PRAM," Symp. VLSI Tech. 2005.
7. J.H. Oh et al, "Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology," IEDM Dig. 2006.