Design of reversible sequential elements with feasibility of transistor implementation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 625-628

  Thapliyal, Himanshu ^a   Vinod, A P ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; FLIP FLOP CIRCUITS; GATES (TRANSISTOR); OPTIMIZATION;

REVERSIBLE LATCHES; REVERSIBLE SEQUENTIAL ELEMENTS; TOFFOLI GATES; TRANSISTOR IMPLEMENTATION;

SEQUENTIAL CIRCUITS;

EID: 34548851499     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378815     Document Type: Conference Paper

References (7)

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3. E. Fredkin, T Toffoli, "Conservative Logic", International Journal of Theor. Physics, vol. 21, nos. 3-4, pp. 219-253, 1982.
4. T. Toffoli., "Reversible Computing", Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science (1980).
5. J.W . Bruce, M.A. Thornton,L. Shivakumariah, P.S. Kokate and X.Li, "Efficient Adder Circuits Based on a Conservative Logic Gate", Proceedings of the IEEE Computer Society Annual Symposium on VLSI(ISVLSI'02), Pittsburgh, PA, USA, April 2002, pp 83-88.
6. Y. Van Rentergem and A. De Vos, " Optimal design of a reversible full adder", Journal of Unconventional Computing, volume 1, pp. 339-355, 2005.
7. J.E Rice, "A New Look at Reversible Memory Elements", Proceedings International Symposium on Circuits and Systems (ISCAS) 2006, Kos, Greece, May 21-24 2006, pp. 243-246