High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2007, Pages

  Ando, T ^a   Hirano, T ^a   Tai, K ^a   Yamaguchi, S ^a   Tanaka, K ^a   Oshiyama, I ^a   Nakata, M ^a   Watanabe, K ^a   Yamamoto, R ^a   Kanda, S ^a   Tateshita, Y ^a   Wakabayashi, H ^a   Tagawa, Y ^a   Tsukamoto, M ^a   Iwamoto, H ^a   Saito, M ^a   Toyoda, S ^b   Kumigashira, H ^b   Oshima, M ^b   Nagashima, N ^a   Kadomura, S ^a   more..

^a SONY CORPORATION   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC VARIABLES MEASUREMENT; ELECTRON MOBILITY; HAFNIUM COMPOUNDS; HOLE MOBILITY; RELIABILITY ANALYSIS; SYNCHROTRON RADIATION;

CRYSTALLIZATION TEMPERATURE; SYNCHROTRON RADIATION PHOTOEMISSION SPECTROSCOPY (SRPES);

GATES (TRANSISTOR);

EID: 34548842757     PISSN: 19308868     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2007.378913     Document Type: Conference Paper

References (11)

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