A 90nm CMOS 16Gb/s transceiver for optical interconnects

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 44-46

  Palermo, Samuel ^a   Emami Neyestanak, Azita ^b   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

^b Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENT CONTROL; OPTICAL INTERCONNECTS; SAMPLING;

BAUD-RATE PHASE; OPTICAL INTERCONNECT TRANSCEIVERS; VCSEL AVERAGE CURRENT;

TRANSCEIVERS;

EID: 34548841391     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373579     Document Type: Conference Paper

References (4)

1. S. Palermo and M. Horowitz, "High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects," Proc. ESSCIRC, pp. 508-511, Sep. 2006.
2. A. Emami-Neyestanak et al., "CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects," Symp. VLSI Circuits, pp. 410-413, June 2004.
3. P. Larsson, "A 2-1600MHz CMOS Clock Recovery PLL with Low-Vdd Capability," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1951-1960, Doc. 1999.
4. S. Sidiropoulos et al., "Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers," Symp. VLSI Circuits, pp. 124-127, June 2000.