Analysis of spurious emission and in-band phase noise of an all digital phase locked loop for RF synthesis using a frequency discriminator

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 3518-3521

  Wicpalek, C ^a   Mayer, T ^b   Maurer, L ^b   Vollenbruch, U ^c   Pittorino, T ^a   Springer, A ^a,c  

^a JOHANNES KEPLER UNIVERSITY LINZ   (Austria)

^b DICE GmbH & Co KG   (Austria)

^c LINZ CENTER OF MECHATRONICS GMBH   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER UTILIZATION; NATURAL FREQUENCIES; PHASE NOISE;

DIGITAL PHASE LOCKED LOOPS; IN-BAND PHASE NOISE; RF SYNTHESIS; SPURIOUS EMISSION;

PHASE LOCKED LOOPS;

EID: 34548828269     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378441     Document Type: Conference Paper

References (6)

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2. I. Galton, "Higher-order delta-sigma frequency-to-digital conversion", Proc. of the IEEE International Symposium on Circuits and Systems, vol. 5, pp 441-444, May 1994.
3. C. Wicpalek, T. Mayer, L. Maurer, U. Vollenbruch, A. Springer, "Analysis of a Two-Bit Frequency Discriminator in an All Digital Phase Locked Loop for RF-Modulation and RF-Frequency Synthesis", Proc. European Conference on Wireless Technology, pp. 273-276, September 2006.
4. M. Hovin, A. Olsen, T. Lande, C. Toumzou, "Delta-Sigma Modulators Using Frequency-Modulated Intermediate Values", IEEE Journal of Solid-State Circuits, vol. 32, no. 1, January 1997.
5. www.3gpp.org, "3GPP TS 45.005 V7.2.0", 3GPP, September 2005
6. www.3gpp.org, "3GPP TS 25.101 V7.4.0", 3GPP, June 2006