RTL-based clock recovery architecture with all-digital duty-cycle correction

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 254-256

  Wang, Ping Ying ^a   Yang, Meng Ta ^a   Chen, Shang Ping ^a   Lin, Meng Hsueh ^a   Yang, Jing Bing ^a  

^a MEDIATEK INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY MULTIPLYING CIRCUITS; PHASE SHIFT; SIGNAL FILTERING AND PREDICTION;

DATA-RATE RANGE; FREQUENCY MULTIPLICATION; PHASE SHIFT CAPABILITY; WRITE-PULSE RECORDING SEQUENCES;

JITTER;

EID: 34548827311     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373390     Document Type: Conference Paper

References (2)

1. Ching-Che Chung, and Chen-Yi Lee, "An ALL-digital Phase-Locked Loop for High-Speed Clock Generation," IEEE J. Solid-State Circuits, vol. 38, pp. 347-351, Feb., 2003.
2. Ping-Ying Wang, et al., "DLL-based Clock Recovery in a PRML Channel," ISSCC Dig. Tech. Papers, pp. 570-571, Feb., 2005.