DLL-based clock recovery in a PRML channel

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Wang, Ping Ying ^a   Kao, Hsueh Wu ^a   Lin, Yung Yu ^a   Yang, Meng Ta ^a   Yang, Jin Bin ^a   Hsieh, Hsiang Ji ^a   Cheng, Yuh ^a   Chen, Chin Yuan ^a   Pan, Jyh Shin ^a  

^a MEDIATEK INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144436569     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. G. Maneatia et al., "Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL," IEEE J. Solid-State Circuits, vol. 38, pp. 1795-1803, Nov., 2003.
2. S. Sidiropoulos and A. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683-1692, Nov., 1997.
3. F. M. Gardner, "Charge-Pump Phase-Lock Loops," IEEE T. Comm., vol. Com-28, pp. 1849-1858, Nov., 1980.
4. AD9888 Data sheet, Analog devices, www.analog.com.