All-CMOS high-speed CML gates with active shunt-peaking

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2554-2557

  Kalantari, Nader ^a   Green, Michael M ^b  

^a Starport Systems   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE NETWORKS; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; HIGH SPEED NETWORKS; OXIDE FILMS;

CURRENT-MODE LOGIC (CML); OXIDE TRANSISTORS; SIMULATION RESULTS; VOLTAGE SUPPLY;

LOGIC GATES;

EID: 34548822458     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.377836     Document Type: Conference Paper

References (4)

1. M. M. Green and U. Singh, "Design of CMOS CML circuits for high-speed broadband communications," in Proc. Int. Symp. on Circuits and Systems, 2003, pp. II-204-II-207.
2. T. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Chap. 8. New York: Cambridge University Press, 1998.
3. E. Sackinger and W. C. Fischer, "A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers," IEEE J. Solid-State Circuits, vol. 35, pp. 1884-1888, Dec. 2000.
4. Behzad Razavi, Design of Integrated Circuits for Optical Communication. New York: McGraw-Hill, 2003.