Flash memory device with 'I' shape floating gate for sub-70 nm NAND flash memory

Japanese Journal of Applied Physics, Part 2: Letters

Volumn 45, Issue 42-45, 2006, Pages

  Jung, Sang Goo ^a   Lee, Jong Ho ^a  

^a Kyungpook National University   (South Korea)

Author keywords

'I' shape; Coupling ratio (CR); Cross talk; Interference; NAND flash; Parasitic capacitance

Indexed keywords

COMPUTER PROGRAMMING; ELECTRIC CURRENT CONTROL; LOGIC GATES; SCALABILITY; THRESHOLD VOLTAGE;

COUPLING RATIO (CR); NAND FLASH; PARASITIC CAPACITANCE; SCALE-DOWNED GEOMETRY;

FLASH MEMORY;

EID: 34548781390     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.45.L1200     Document Type: Article

References (7)

1. Y. S. Hisamune, K, Kanamori, T. Kubota, Y. Suzuki, M. Tsukiji, E. Hasegawa, A. Ishitani and T. Okazawa: IEDM Tech. Dig., 1993, p. 19.
2. H. Shirai, T. Kubota, I. Honma, H. Watanabe, H. Ono and T. Okazawa: IEDM Tech. Dig., 1995, p. 653.
3. T. Kitamura, M. Kawata, I. Honma, I. Yamamoto, S. Nishimoto and K. Oyama: VLSI Tech. Dig., 1.998, p. 104.
4. T.-K. Kim, J. Song, D. Oh, C. Lee, T. Jang, J. Lim, D. Lee, S. Lee, M. Lim, B. Park, M. Lee, S. Jo, W. Lee, J. Choi and K. Kim: Korean Conf. Semiconductors, 2006, Vol. 13, p. 103.
5. J.-G. Kim, J.-Y. Ahn, H.-S. Kim, J.-W. Lim, C.-H. Kim, H. Shu, K. Hasebe, S.-H. Hur, J.-H. Park, H.-S. Kim, Y.-G. Shin, U. Chung and J.-T. Moon: IEDM Tech. Dig., 2004, p. 1063.
6. M. Momodomi, T. Tanaka, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R, Shirota, K. Ohuchi and F. Masuoka: IEEE J. Solid-State Circuits 26 (1991) 492.
7. J.-D. Lee, S.-H. Hur and J.-D. Choi: IEEE Electron Device Lett. 23 (2002) 264.