Integrated row and column rerouting for reconfiguration of VLSI arrays with four-port switches

IEEE Transactions on Computers

Volumn 56, Issue 10, 2007, Pages 1387-1400

  Jigang, Wu ^a   Srikanthan, Thambipillai ^a   Wang, Xiaodong ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Algorithm; Degradable VLSI array; Fault tolerance; Reconfiguration; Routing

Indexed keywords

ERROR COMPENSATION; FAULT TOLERANCE; ROUTING ALGORITHMS;

FAULTY PROCESSIG ELEMENT; MAXIMAL SQUARE TARGET ARRAY;

VLSI CIRCUITS;

EID: 34548776419     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.1085     Document Type: Article

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