A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors

IEEE Transactions on Computers

Volumn 46, Issue 12, 1997, Pages 1363-1371

  Chen, Yung Yuan ^a   Upadhyaya, Shambhu J ^b,c   Cheng, Ching Hwa ^a  

^a CHUNG HUA UNIVERSITY   (Taiwan)

^b UNIVERSITY AT BUFFALO   (United States)

^c IEEE   (United States)

Author keywords

Performance analysis; Reconfiguration process; Redundancy scheme; Switch programming; VLSI WSI array processor; Yield simulation

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; COMPUTER PROGRAMMING; COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; FAULT TOLERANT COMPUTER SYSTEMS; PERFORMANCE; PROBABILITY; SOFTWARE ENGINEERING; SWITCHING CIRCUITS; WSI CIRCUITS;

RECONFIGURATION PROCESS; REDUNDANCY SCHEME; SWITCH PROGRAMMING;

PARALLEL PROCESSING SYSTEMS;

EID: 0031366107     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.641936     Document Type: Article

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