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Volumn , Issue , 2007, Pages 618-623

An algorithm to minimize leakage through simultaneous input vector control and circuit modification

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUITS;

EID: 34548348854     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364662     Document Type: Conference Paper
Times cited : (16)

References (8)
  • 2
    • 1642414282 scopus 로고    scopus 로고
    • Leakage current reduction in CMOS VLSI circuits by input vector control
    • A. Abdollahi, F. Fallah, and M. Pedram. Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Trans. VLSI Syst., 12(2): 140-154, 2004.
    • (2004) IEEE Trans. VLSI Syst , vol.12 , Issue.2 , pp. 140-154
    • Abdollahi, A.1    Fallah, F.2    Pedram, M.3
  • 3
  • 4
    • 34547206809 scopus 로고    scopus 로고
    • A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction
    • L. Cheng, L. Deng, D. Chen, and M. D. F. Wong. A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. In DAC, pages 117-120, 2006.
    • (2006) DAC , pp. 117-120
    • Cheng, L.1    Deng, L.2    Chen, D.3    Wong, M.D.F.4
  • 5
    • 0030712582 scopus 로고    scopus 로고
    • A gate-level leakage power reduction method for ultra low power CMOS circuits
    • J. Halter and F. Najm. A gate-level leakage power reduction method for ultra low power CMOS circuits. In Proceedings of CICC, pages 475-478, 1997.
    • (1997) Proceedings of CICC , pp. 475-478
    • Halter, J.1    Najm, F.2
  • 8
    • 27944438871 scopus 로고    scopus 로고
    • Enhanced leakage reduction technique by gate replacement
    • L. Yuan and G. Qu. Enhanced leakage reduction technique by gate replacement. In DAC, pages 47-50, 2005.
    • (2005) DAC , pp. 47-50
    • Yuan, L.1    Qu, G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.