Methodology for fast SPICE simulation of frequency synthesizers

IEEE Circuits and Devices Magazine

Volumn 16, Issue 4, 2000, Pages 10-15

  Tang, Yiwu ^a   Ismail, Mohammed ^a  

^a OHIO STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SOFTWARE; FLIP FLOP CIRCUITS; FREQUENCY DIVIDING CIRCUITS; LOGIC GATES; PHASE LOCKED LOOPS; TRANSISTORS; VARIABLE FREQUENCY OSCILLATORS;

CHARGE PUMPS; LOOP FILTERS; MIXED-MODE SIMULATION; PHASE FREQUENCY DETECTORS (PFD); SOFTWARE PACKAGE SPICE;

FREQUENCY SYNTHESIZERS;

EID: 0034224083     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.857745     Document Type: Article

References (10)

1. J.P. Hein and J.W. Scott, "Z-domain model for discrete-time PLL's," IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 1393-1400, Nov. 1988.
2. D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, chapt. 16, 1997.
3. E. Liu and A.L. Sangiovanni-Vincentelli, "Behavioral representations for VCO and detectors in phase-lock systems," in Proc. CICC, 1992, paper 12.3.
4. A. Demir, E. Liu, A.L. Sangiovanni-Vincentelli, and I. Vassiliou, "Behavioral simulation techniques for phase/delay-locked systems," in Proc. CICC, 1994, paper 21.3.
5. W. Current, J. Parker, and W. Hardaker, "Behavioral modeling of analogue and mixed-signal circuits for efficient computer-aided design," Int. J. Electronics, vol. 80, no. 1, pp. 63-76, 1996.
6. A. Phanse, "Behavioral modeling of a phase locked loop," in Proc. 1996 Southcon Conference, Orlando, FL, 1996, pp. 400-404.
7. X. Li and M. Ismail, "Fast simulation of sigma-delta modulators using SPICE," IEEE Circuits and Devices Mag., vol. 15, no. 1, pp. 7-9, Jan. 1999.
8. M. Sitkowski, "Simulation modeling: The macro modeling of phase locked loops for the Spice simulator," IEEE Circuits and Devices Mag., vol. 7, no. 2. pp. 11-15, Mar. 1991.
9. R.E. Best, Phase Locked Loops: Theory, Design, and Applications. 2nd Ed. New York: McGraw-Hill, 1993.
10. B. Razavi, Ed., Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. Piscataway, NJ: IEEE Press, 1996.