Product specific sub-micron E-fuse reliability and design qualification

IEEE International Integrated Reliability Workshop Final Report

Volumn 2003-January, Issue , 2003, Pages 36-40

  Tont, W Ri ^a   Fifield, J A ^b   Higgins, J ^b   Guthrie, W H ^b   Berry, W ^b   Narayan, C ^c  

^a IBM   (United States)

^b IBM MICROELECTRONICS   (United States)

^c IBM RESEARCH   (United States)

Author keywords

Bonding; CMOS technology; Fuses; Latches; Microelectronics; Neck; Packaging; Qualifications; Reliability engineering; Rivers

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT DESIGN; POLYCRYSTALLINE MATERIALS; RELIABILITY; SILICIDES;

BONDING; CMOS TECHNOLOGY; DESIGN QUALIFICATIONS; LASER FUSE; LATCH; NECK; QUALIFICATION; RELIABILITY (ENGINEERING); RELIABILITY QUALIFICATION; SUBMICRON;

MICROELECTRONICS;

EID: 34548273827     PISSN: 19308841     EISSN: 23748036     Source Type: Conference Proceeding    
DOI: 10.1109/IRWS.2003.1283296     Document Type: Conference Paper

References (11)

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4. A. Kalnitsky, I Saadat, A Bergemont, P Francis: CoSi2 integrated fuses on polysilicon for low voltage 0.18um CMOS applications, 1999 IEDM
5. JESD-22A113, Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
6. JESD-22 A108, Temperature, Bias, and Operating Life
7. JESD-22 A104, Temperature Cycling
8. JESD-22 A110, Highly Accelerated Temperature and Humidity Stress Test (HAST)
9. EIA Bulletin SSB-1
10. JEP-122, Failure Mechanisms and Models for Silicon Semiconductor Devices
11. U.S. patent pending.