On-the-fly sending : A low latency high bandwidth message transfer mechanism

Proceedings - International Symposium on Parallel Architectures, Algorithms, and Networks, I-SPAN 2000

Volumn , Issue , 2000, Pages 186-193

  Tanabe, Noboru ^a   Yamamoto, Junji ^a   Nishi, Hiroaki ^a   Kudoh, Tomohiro ^a   Hamada, Yoshihiro ^b   Nakajo, Hironori ^b   Amano, Hideharu ^c  

^a RWCP Tsukuba Research Center Mitsui Building Tsukuba   (Japan)

^b TOKYO UNIVERSITY OF AGRICULTURE AND TECHNOLOGY   (Japan)

^c KEIO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTERFACES (COMPUTER); MEMORY ARCHITECTURE; NEGATIVE IMPEDANCE CONVERTERS; NETWORK ARCHITECTURE; PERSONAL COMPUTERS;

CPU CYCLES; HIGH BANDWIDTH; HIGH-BANDWIDTH NETWORKS; LOW LATENCY; MEMORY SLOTS; MESSAGE TRANSFERS; NETWORK INTERFACE ARCHITECTURE; NETWORK INTERFACE CARDS; NETWORK INTERFACE CONTROLLERS; TRANSFER MECHANISMS;

BANDWIDTH;

EID: 34548258548     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPAN.2000.900284     Document Type: Conference Paper

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