Multiplication over Fpm on FPGA: A survey

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4419 LNCS, Issue , 2007, Pages 214-225

  Beuchat, Jean Luc ^a   Miyoshi, Takanori ^a   Oyama, Yoshihito ^a   Okamoto, Eiji ^a  

^a UNIVERSITY OF TSUKUBA   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC PROGRAMMING; GATES (TRANSISTOR); POLYNOMIALS; PROGRAM COMPILERS;

ARCHITECTURAL PARAMETERS; IRREDUCIBLE POLYNOMIALS; MULTIPLICATION ALGORITHMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548093247     PISSN: 03029743     EISSN: 16113349     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. P. S. L. M. Barreto. A note on efficient computation of cube roots in characteristic 3. Cryptology ePrint Archive, Report 2004/305, 2004.
2. m) arithmetic architectures for cryptographic applications. In M. Joye, editor, Topics in Cryptology - CT-RSA 2003, number 2612 in Lecture Notes in Computer Science, pages 158-175. Springer, 2004.
3. J.-L. Beuchat, M. Shirase, T. Takagi, and E. Okamoto. An algorithm for the η pairing calculation in characteristic three and its hardware implementation. Cryptology ePrint Archive, Report 2006/327, 2006.
4. m). Acta Applicandae Mathematicae, 93(1-3):33-55, September 2006.
5. P. Grabher and D. Page. Hardware acceleration of the Tate Pairing in characteristic three. In J. R. Rao and B. Sunar, editors, Cryptographic Hardware and Embedded Systems - CHES 2005, number 3659 in Lecture Notes in Computer Science, pages 398-411. Springer, 2005.
6. J. Guajardo, T. Güneysu, S. Kumar, C. Paar, and J. Pelzl. Efficient hardware implementation of finite fields with applications to cryptography. Acta Applicandae Mathematicae, 93(1-3):75-118, September 2006.
7. T. Kerins, W. P. Marnane, E. M. Popovici, and P.S.L.M. Barreto. Efficient hardware for the Tate Pairing calculation in characteristic three. In J. R. Rao and B. Sunar, editors, Cryptographic Hardware and Embedded Systems - CHES 2005, number 3659 in Lecture Notes in Computer Science, pages 412-426. Springer, 2005.
8. T. Kerins, E. Popovici, and W. Marnane. Algorithms and architectures for use in FPGA implementations of identity based encryption schemes. In J. Becker, M. Platzner, and S. Vernalde, editors, Field-Programmable Logic and Applications, number 3203 in Lecture Notes in Computer Science, pages 74-83. Springer, 2004.
9. m) multipliers for curve-based cryptography. IEEE Transactions on Computers, 55(10):1306-1311, October 2006.
10. R. Ronan, C. Ó hÉigeartaigh, C. Murphy, M. Scott, T. Kerins, and W.P. Marnane. An embedded processor for a pairing-based cryptosystem. In Proceedings of the Third International Conference on Information Technology: New Generations (ITNG'06). IEEE Computer Society, 2006.
11. C. Shu, S. Kwon, and K. Gaj. FPGA accelerated Tate pairing based cryptosystem over binary fields. Cryptology ePrint Archive, Report 2006/179, 2006.
12. L. Song and K. K. Parhi. Low energy digit-serial/parallel finite field multipliers. Journal of VLSI Signal Processing, 19(2): 149-166, July 1998.