Two complementary approaches for studying the effects of SEUs on digital processors

IEEE Transactions on Nuclear Science

Volumn 54, Issue 4, 2007, Pages 924-928

  Valderas, Mario García ^a,b   Peronnard, Paul ^c   Ongil, Celia López ^a,b   Ecoffet, Robert ^d   Bezerra, Françoise ^d   Velazco, Raoul ^a,c  

^a IEEE

^b UNIVERSIDAD CARLOS III DE MADRID   (Spain)

^c TlMA Laboratory   (France)

^d CNES   (France)

Author keywords

Fault injection; Fault tolerance; FPGA emulation; SEU

Indexed keywords

DATA STORAGE EQUIPMENT; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLIP FLOP CIRCUITS;

CODE EMULATED UPSET; DIGITAL PROCESSORS; FAULT INJECTION; LEON PROCESSOR;

PROGRAM PROCESSORS;

EID: 34548078901     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.893871     Document Type: Conference Paper

References (11)

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