A low power and low signal 5-bit 25 MS/s pipelined ADC for monolithic active pixel sensors

IEEE Transactions on Nuclear Science

Volumn 54, Issue 4, 2007, Pages 1195-1200

  Bouvier, J ^b   Dahoumane, Mokrane ^b   Dzahini, Daniel ^a,b   Hostachy, J Y ^b   Lagorio, E ^b   Rossetto, O ^b   Ghazlane, Hamid ^c   Dallet, Dominique ^d  

^a IEEE

^b UNIVERSITÉ JOSEPH FOURIER GRENOBLE 1   (France)

^c CENTRE NATIONAL DE L ENERGIE DES SCIENCES TECHNIQUES NUCLEAIRES   (Morocco)

^d UNIVERSITÉ BORDEAUX 1   (France)

Author keywords

1.5 bits per stage; Low power; MAPS tracker; Pipelined ADC; Pixel sensors; Switched capacitor design

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; PIXELS; READOUT SYSTEMS; SENSORS;

MAPS TRACKER; PIPELINED ADC; PIXELS SENSOR; VERTEX DETECTOR; VOLTAGE DISPERSION;

ANALOG TO DIGITAL CONVERSION;

EID: 34548058839     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.903175     Document Type: Conference Paper

References (8)

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