10-bit, 20-MS/s, 35-mW pipeline A/D converter

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1994, Pages 499-501

  Cho, Thomas B ^a   Gray, Paul R ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; DIGITAL TO ANALOG CONVERSION; ENERGY DISSIPATION; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; NYQUIST DIAGRAMS; PIPELINE PROCESSING SYSTEMS; SIGNAL TO NOISE RATIO;

CAMCORDERS; COMMUNICATION DEVICES; DEGRADATION OF LINEARITY; DIGITAL CORRECTION; HIGH SPEED SAMPLING; NYQUIST SAMPLING; PIPELINED CONFIGURATION; QUANTIZATION; SAMPLE HOLD FUNCTION; SWITCHED CAPACITOR CIRCUIT;

ANALOG TO DIGITAL CONVERSION;

EID: 0028123971     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)