WADE: A Web-based automated parallel CAD environment

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 1998, Pages 473-480

  Chakrabarti, D R ^a   Joisha, P G ^a   Chandy, J A ^b   Krishnaswamy, D ^c   Krishnaswamy, V ^c   Banerjee, P ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

^b Sierra Vista Research   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

WEBSITES;

DESIGN AND TESTS; FAULT SIMULATORS; PARALLEL ENVIRONMENT; PARALLEL MACHINE; PLACEMENT TOOLS; REMOTE MACHINES; SCHEDULING TOOLS; STANDARD INTERFACE;

COMPUTER AIDED DESIGN;

EID: 34547670768     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HIPC.1998.738024     Document Type: Conference Paper

References (15)

1. Richard Newton, URL http://www-cad.eecs.berkeley.edu/Respep/Research/weld.
2. URL http://snf.stanford.edu/staff/losleben
3. D. Lidsky and J.M. Rabaey, Early Power Exploration-A World Wide Web Application, 33rd Design Automation Conference, Las Vegas, 1996, NY, USA. (URL http://infopad.eecs.berkeley.edu/PowerPlay)
4. URL http://agamemnon.stanford.edu/levitt/vc.html
5. URL http://speedie.stanford.edu
6. Shankar Subramaniam, Biology Workbench, URL http://bioweb.ncsa.uiuc.edu.
7. D. Saha and A. P. Chandrakasan, Web-based Distributed VLSI Design, The 11th International Conference on VLSI Design, January 4-7, 1998, Chennai, India.
8. P. Banerjee, Parallel Algorithms for VLSI Computer-Aided Design, Prentice-Hall, Inc., Englewoods-Cliffs, NJ, 1994.
9. J. A. Chandy and P. Banerjee, A Parallel Circuit-Partitioned Algorithm for Timing Driven Standard Cell Placement, Proc. Int. Conf. on Computer Design (ICCD 97), October 1997, Austin, TX.
10. L. A. Sanchis, Multiple-way Network Partitioning, IEEE Transactions on Computers, 38:62-81, 1989.
11. D. Krishnaswamy, E. Rudnick and P. Banerjee, SPITFIRE: Scalable Parallel Algorithms for Test Set Partitioned Fault Simulation, Proc. of IEEE VLSI Test Symposium, Monterey, CA, April 1997.
12. V. Krishnaswamy, P. Banerjee, Parallel Compiled Event Driven VHDL Simulation, To appear in The 12th International Conference on Supercomputing, July 1998 (ICS98), Melbourne, Australia.
13. V. Krishnaswamy, G. Hasteer and P. Banerjee, Load Balancing and Work Load Minimization of Overlapping Parallel Tasks, Proceedings of the International Conference on Parallel Processing, August 11-15, 1997.
14. URL http://www.ics.uci.edu/pub/ieff/html/rfc1867.txt
15. S. Hauck and S. Knol, Data Security for Web-based CAD, Design Automation Conference, 1998.