Efficient computation of buffer capacities for cyclo-static dataflow graphs

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 658-663

  Wiggers, Maarten H ^a   Bekooij, Marco J G ^b   Smit, Gerard J M ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Buffer capacity; Dataflow; System on chip

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER RESOURCE MANAGEMENT; DATA FLOW ANALYSIS; MULTIPROCESSING SYSTEMS; REAL TIME SYSTEMS; STORAGE ALLOCATION (COMPUTER);

BUFFER CAPACITY; CYCLO-STATIC DATAFLOW GRAPHS; SYSTEM-ON-CHIP; THROUGHPUT CONSTRAINT;

BUFFER STORAGE;

EID: 34547370488     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375247     Document Type: Conference Paper

References (12)

1. M. J. G. Bekooij et al. Dataflow Analysis for Real-Time Embedded Multiprocessor System Design, chapter 15. Dynamic and Robust Streaming Between Connected CE Devices. Kluwer Academic Publishers, 2005.
2. D. Bertsimas and J. N. Tsitsiklis. Introduction to Linear Optimization. Athena Scientific, 1997.
3. G. Bilsen et al. Cyclo-Static Dataflow. IEEE Transactions on Signal Processing, 44(2):397-408, February 1996.
4. A. Dasdan. Experimental Analysis of the Fastest Optimum Cycle Ratio and Mean Algorithms. ACM Transactions on Design Automation of Embedded Systems, 9(4):385-418, October 2004.
5. R. Govindarajan et al. Minimizing Buffer Requirement under Rate-Optimal Schedules in Regular Dataflow Networks. Journal of VLSI Signal Processing, 31(3), 2002.
6. E. A. Lee and D. G. Messerschmitt. Synchronous Dataflow. Proceedings of the IEEE, 75(9):1235-1245, September 1987.
7. C. W. Mercer et al. Processor Capacity Reserves: Operating System Support for Multimedia Applications. In Proc. IEEE Int'l Conference on Multimedia Computing and Systems, pages 90-99, 1994.
8. T. M. Parks et al. A Comparison of Synchronous and Cyclo-Static Dataflow. In Proc. IEEE Asilomar Conference on Signals, Systems and Computers, pages 204-210, October 1995.
9. J. L. Pino and E. A. Lee. Hierarchical Static Scheduling of Dataflow Graphs onto Multiple Processors. In Proc. IEEE Int'l Conference on Acoustics, Speech, and Signal Processing, May 1995.
10. S. Sriram and S.S. Bhattacharyya. Embedded Multiprocessors: Scheduling and Synchronization. Marcel Dekker Inc., 2000.
11. S. Stuijk et al. Exploring Trade-Offs in Buffer Requirements and Throughput Constraints for Synchronous Dataflow Graphs. In Proc. Design Automation Conference (DAC), pages 889-904, July 2006.
12. M. H. Wiggers et al. Efficient Computation of Buffer Capacities for Multi-Rate Real-Time Systems with Back-Pressure. In Proc. Int'l Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2006.