A power planning model for implantable stimulators

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 2925-2928

  Hashemi, S ^a   Sawan, M ^a   Savaria, Y ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; ENERGY DISSIPATION; MATHEMATICAL MODELS; PARAMETER ESTIMATION;

CIRCUIT MODULES; DESIGN PARAMETERS; POWER CONVERSION CHAINS (PCC); POWER ESTIMATION;

CIRCUIT SIMULATION;

EID: 34547368952     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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6. th ed., Oxford University Press, 1998.
7. P. Favrat, P. Deval, and M.J. Declercq, "A high-efficiency CMOS voltage doubler," IEEE J. Solid-State Circuits, Vol. 33, No. 3, pp. 410-416, Mar. 1998.