A VHDL model and implementation of a coarse-grain reconfigurable coprocessor for a RISC core

PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings

Volumn , Issue , 2006, Pages 229-232

  Brunelli, Claudio ^a   Cinelli, Federico ^b   Rossi, Davide ^a   Nurmi, Jari ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CIRCUIT SIMULATION; COMPUTATIONAL METHODS; COMPUTER SOFTWARE; MATHEMATICAL MODELS; MULTIMEDIA SYSTEMS; SIGNAL PROCESSING;

MULTIMEDIA APPLICATIONS; OPERATING FREQUENCY; RECONFIGURABLE COPROCESSORS; VHDL MODELS;

REDUCED INSTRUCTION SET COMPUTING;

EID: 34547339219     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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8. A Flexible, Low Power, High Performance DSP IP Core for Programmable Systems-on-Chip. http://www.us.design-reuse.com/articles/article12159.html
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