Logic optimization for majority gate-based nanoelectronic circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 1307-1310

  Huo, Zhi ^a   Zhang, Qishan ^a   Haruehanroengra, Sansiri ^b   Wang, Wei ^b  

^a BEIHANG UNIVERSITY   (China)

^b Indiana University Purdue University Indianapolis   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR AUTOMATA; ELECTRON TUNNELING; GATES (TRANSISTOR); OPTIMIZATION;

NANOELECTRONIC CIRCUITS; OPTIMIZER; SINGLE ELECTRON TUNNELING CIRCUIT DESIGN; TUNNELING PHASE LOGIC;

NANOELECTRONICS;

EID: 34547291881     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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