Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 229-234

  Zhang, Rui ^a   Gupta, Pallav ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN LOGIC; QUANTUM CELLULAR AUTOMATA (QCA); SINGLE ELECTRON TUNNELING (SET); TUNNELING PHASE LOGIC (TPL);

AUTOMATA THEORY; BOOLEAN ALGEBRA; CELLULAR RADIO SYSTEMS; ELECTRON TUNNELING; FORMAL LOGIC;

QUANTUM THEORY;

EID: 27944457251     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. "Semiconductor Industries Association Roadmap." http://public.itrs.net
2. M. T. Niemier, M. J. Kontz, and P. M. Kogge, "A design of and design tools for a novel quantum dot based microprocessor," in Proc. Design Automation Conf., June 2000, pp. 227-232.
3. D. Berzon and T. J. Fountain, "A memory design in QCAs using the SQUARES formalism," in Proc. ACM Great Lakes Symp. VLSI, Mar. 1999, pp. 166-169.
4. N. Gergel, S. Craft, and J. Lach, "Modeling QCA for area minimization in logic synthesis," in Proc. ACM Great Lakes Symp. VLSI, Apr. 2003, pp. 60-63.
5. H. A. Fahmy and R. A. Kiehl, "Complete logic family using tunneling-phase-logic devices," in Proc. Int. Conf. Microelectronics, Nov. 1999, pp. 22-24.
6. T. Oya, T. Asai, T. Fukui, and Y. Amemiya, "A majority-logic device using an irreversible single-electron box," IEEE Trans. Nanotechnol., vol. 2, no. 1, pp. 15-22, Mar. 2003.
7. P. D. Tougaw and C. S. Lent, "Logical devices implemented using quantum cellular automata," J. Applied Physics, vol. 75, no. 3, pp. 1818-1825, Feb. 1994.
8. Z. Yu, R. W. Dutton, and R. A. Kiehl, "Circuit/device modeling at the quantum level," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1819-1825, Oct. 2000.
9. G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms. Norwell, MA: Kluwer Academic Publishers, 1998.
10. Z. Kohavi, Switching and Finite Automata Theory. New York, NY: McGraw-Hill, 1978.
11. S. B. Akers, "Synthesis of combinational logic using three-input majority gates," in Proc. Third Annual Symp. Switching Circuit Theory & Logical Design, Oct. 1962, pp. 149-157.
12. H. S. Miller and R. O. Winder, "Majority logic synthesis by geometric methods," IRE Trans. Electronic Computers, vol. EC-11, no. 1, pp. 89-90, Feb. 1962.
13. S. Muroga, Threshold Logic and its Applications. New York, NY: John Wiley, 1971.
14. E. M. Sentovich et al., "Sequential circuit design using synthesis and optimization," in Proc. Int. Conf. Computer Design, Oct. 1992, pp. 328-333.
15. R. Lisanke, "Logic synthesis and optimization benchmarks," Microelectronics Center of North Carolina, Tech. Rep., 1988.